1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device, and more particularly to a manufacturing method of a semiconductor device in which damage of a gate oxide film due to charge-up phenomenon in a reactive ion etching method can be reduced when wirings are formed.
2. Description of Related Art
In a conventional semiconductor device, in order to perform anisotropic etching to a wiring film composed of material of aluminium or the like, a reactive ion etching (RIE) method is generally used, because of excellent perpendicular workability and fine fabrication. In the reactive ion etching method, ions generated in plasma are used. Therefore, electrons, positive charge ions, negative charge ions are contained in an ambience. In a case where the semiconductor devices such as a MOS-type field effect transistor are manufactured to have a gate electrode, these electrically charged particles flow into the gate electrode through a contact during the etching process. As a result, since high voltage is applied to the gate electrode, a thin gate oxide film is sometimes degraded and destroyed. The problem is called plasma damage and is one of the causes that the reliability is reduced when the semiconductor device is manufactured. The larger the lateral area of the wiring pattern connected to the gate electrode is, the more conspicuous this plasma damage is.
In a case where a metal wiring pattern is formed by use of the reactive ion etching method, various manufacturing methods are proposed to prevent the plasma damage of the gate oxide film in the plasma process. For example, as shown in the technique of FIG. 1, which is described in Japanese Laid Open Patent Disclosure (JP-A-Showa 63-25976), a protection diode is previously formed by layers 22 and 27, and a gate electrode 25 under a contact hole 29a is connected to the protection diode. Therefore, the electric charges generated when a through hole 30 is formed by the plasma etching process are directed to a silicon substrate 21 through the protection diode. This protection diode is also effective when a wiring film is etched to form a wiring pattern. The wiring pattern to be formed is connected to the protection diode via the contact hole 30 and the gate electrode 25. For this reason, charging up of the gate electrode can be restrained.
On the other hand, the method is proposed in which the plasma damage is reduced by adding a new manufacturing process without adding a functional element like the protection diode. FIGS. 2A to 2C are plan views illustrating the processes of the manufacturing method of the semiconductor device which is described in Japanese Laid Open Patent Disclosure (JP-A-Heisei 5-343398). In this method, an aluminium film is connected to a gate electrode through a contact 41. First, as shown in FIG. 2A, the aluminium film is etched by the reactive ion etching method using a photoresist as a mask such that a pattern 42 is removed. As a result, patterns 43a and 43b are left. The pattern 43a is connected to the gate electrode through the contact hole 41. In this case, the etching is performed such that the gate electrode is not charged up, i.e., such that the area of the pattern 42 becomes as small as possible.
Next, as shown in FIG. 2B, the aluminum film other than the pattern 43a is etched by the reactive ion etching using a photoresist as a mask so as to form wiring patterns 44. In this case, the pattern 43a on the contact hole 41 is separated from the aluminium wiring patterns 44. Also, because the surface area of the pattern 43a is very small, the injection of charged particles into the gate electrode can be restrained.
Finally, as shown in FIG. 2C, a tungsten film 45 is deposited by use of a selective CVD method such that separated aluminium wiring patterns are connected to each other. In this way, a wiring pattern is completed.
However, as described below, there are problems in the above-mentioned conventional manufacturing methods of the semiconductor device. First, in the conventional manufacturing method which is shown in FIG. 1, because the protection diode must be always formed, the required layout area increase. As a result, an integration density decreases. Also, because the wiring patterns must be always connected to either protection diode, the design of a circuit is greatly constrained.
On the other hand, in the conventional manufacturing method which is shown in FIGS. 2A to 2C, the lithography process needs to be executed many times, so that the manufacturing process becomes complicated. Therefore, it is difficult to reduce the number of manufacturing processes, and it is also difficult to avoid the rise of cost. Also, because an isolation pattern on the contact hole and patterns other than the isolation pattern are connected after the wiring film is patterned, a short circuit is easily produced in the high-density integrated circuit in which the separation between the wiring patterns is narrow, when the tungsten film is formed.
That is, these conventional techniques are not suitable for formation of fine patterns and high density integration.